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80C88
March 1997
CMOS 8/16-Bit Microprocessor
Description
The Intersil 80C88 high performance 8/16-bit CMOS CPU is manufactured using a self-aligned silicon gate CMOS process (Scaled SAJI IV). Two modes of operation, MINimum for small systems and MAXimum for larger applications such as multiprocessing, allow user configuration to achieve the highest performance level. Full TTL compatibility (with the exception of CLOCK) and industry-standard operation allow use of existing NMOS 8088 hardware and Intersil CMOS peripherals. Complete software compatibility with the 80C86, 8086, and 8088 microprocessors allows use of existing software in new designs.
Features
* Compatible with NMOS 8088 * Direct Software Compatibility with 80C86, 8086, 8088 * 8-Bit Data Bus Interface; 16-Bit Internal Architecture * Completely Static CMOS Design - DC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5MHz (80C88) - DC . . . . . . . . . . . . . . . . . . . . . . . . . . . .8MHz (80C88-2) * Low Power Operation - ICCSB . . . . . . . . . . . . . . . . . . . . . . . . 500A Maximum - ICCOP . . . . . . . . . . . . . . . . . . . . 10mA/MHz Maximum * 1 Megabyte of Direct Memory Addressing Capability * 24 Operand Addressing Modes * Bit, Byte, Word, and Block Move Operations * 8-Bit and 16-Bit Signed/Unsigned Arithmetic * Bus-Hold Circuitry Eliminates Pull-up Resistors * Wide Operating Temperature Ranges - C80C88 . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to + 70oC - I80C88 . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC - M80C88 . . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC
[ /Title (80C88 ) /Subject CMO 8/16it icrorocesor) /Autho () /Keyords Interil orpoation, /16 it uP, icrorocesor, 8 it, 16 it, 8it, 16it, 088, C) /Cretor ()
Ordering Information
PACKAGE Plastic DIP TEMPERATURE RANGE 0oC to +70oC -40oC to +85oC PLCC 0oC to +70oC -40oC to +85oC CERDIP 0oC to +70oC -40oC to +85oC -55oC to +125oC SMD# LCC SMD# -55oC to +125oC -55oC to +125oC -55oC to +125oC CP80C88 IP80C88 CS80C88 lS80C88 CD80C88 ID80C88 MD80C88/B 5962-8601601QA MR80C88/B 5962-8601601XA 5MHz 8MHz CP80C88-2 IP80C88-2 CS80C88-2 IS80C88-2 CD80C88-2 ID80C88-2 MD80C88-2/B MR80C88-2/B PKG. NO. E40.6 E40.6 N44.65 N44.65 F40.6 F40.6 F40.6 F40.6 J44.A J44.A
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
File Number
2949.1
3-1
80C88 Pinouts
80C88 (DIP) TOP VIEW
GND A14 A13 A12 A11 A10 A9 A8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 NMI INTR CLK GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 MIN MODE 40 VCC 39 A15 38 A16/S3 37 A17/S4 36 A18/S5 35 A19/S6 34 SS0 33 MN/MX 32 RD 31 HOLD 30 HLDA 29 WR 28 IO/M 27 DT/R 26 DEN 25 ALE 24 INTA 23 TEST 22 READY 21 RESET (RQ/GT0) (RQ/GT1) (LOCK) (S2) (S1) (S0) (QS0) (QS1) (HIGH) MAX MODE
80C88 (PLCC/LCC) TOP VIEW
A16/S3 A16/S3 A17/S4 A18/S5 A17/S4 A18/S5 39 38 37 36 35 34 33 32 31 30 29 18 19 20 21 22 23 24 25 26 27 28 READY RESET TEST INTR INTA GND CLK ALE NMI MIN MODE 80C88 MAX MODE 80C88 GND
VCC VCC
A11
A12
A13
A14
MAX MODE 80C88 A11 A12 A13 A14
GND
MIN MODE 80C88 A10 A9 A8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 A10 A9 A8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 7 8 9 10 11 12 13 14 15 16 17
6
5
4
3
2
1 44 43 42 41 40 NC A19/S6 SS0 MN/MX RD HOLD HLDA WR IO/M DT/R DEN NC A19/S6 (HIGH) MN/MX RD RQ/GT0 RQ/GT1 LOCK S2 S1 S0
NC
NC
READY
RESET
A15
NC
A15
NC
TEST
INTR
GND
CLK
QS1
3-2
QS0
NMI
NC
NC
80C88 Functional Diagram
EXECUTION UNIT REGISTER FILE DATA POINTER AND INDEX REGS (8 WORDS) BUS INTERFACE UNIT RELOCATION REGISTER FILE SEGMENT REGISTERS AND INSTRUCTION POINTER (5 WORDS)
SSO/HIGH 16-BIT ALU FLAGS BUS INTERFACE UNIT 8 8 3 4 4 A19/S6. . . A16/S3 AD7-AD0 A8-A15 INTA, RD, WR DT/R, DEN, ALE, IO/M
4-BYTE INSTRUCTION QUEUE TEST INTR NMI RQ/GT0, 1 HOLD HLDA 3 RESET READY MN/MX GND VCC 2 CONTROL AND TIMING LOCK 2 3 QS0, QS1 S2, S1, S0
CLK
MEMORY INTERFACE C-BUS
B-BUS ES BUS INTERFACE UNIT CS SS DS IP
INSTRUCTION STREAM BYTE QUEUE
EXECUTION UNIT CONTROL SYSTEM A-BUS
AH BH CH EXECUTION UNIT DH SP BP SI DI
AL BL CL DL
ARITHMETIC/ LOGIC UNIT
FLAGS
3-3
80C88 Pin Description
The following pin function descriptions are for 80C88 systems in either minimum or maximum mode. The "local bus" in these descriptions is the direct multiplexed bus interface connection to the 80C88 (without regard to additional bus buffers).
SYMBOL AD7-AD0 PIN NUMBER 9-16 TYPE I/O DESCRIPTION ADDRESS DATA BUS: These lines constitute the time multiplexed memory/IO address (T1) and data (T2,T3,Tw and T4) bus. These lines are active HIGH and are held at high impedance to the last valid level during interrupt acknowledge and local bus "hold acknowledge" or "grant sequence" ADDRESS BUS: These lines provide address bits 8 through 15 for the entire bus cycle (T1-T4). These lines do not have to be latched by ALE to remain valid. A15-A8 are active HIGH and are held at high impedance to the last valid logic level during interrupt acknowledge and local bus "hold acknowledge" or "grant sequence". ADDRESS/STATUS: During T1, these are the four most significant address lines for memory operations. During I/O operations, these lines are LOW. During memory and I/O operations, status information is available on these lines during T2, T3, TW and T4. S6 is always LOW. The status of the interrupt enable flag bit (S5) is updated at the beginning of each clock cycle. S4 and S3 are encoded as shown. This information indicates which segment register is presently being used for data accessing. These lines are held at high impedance to the last valid logic level during local bus "hold acknowledge" or "grant Sequence". S4 0 0 1 1 S3 0 1 0 1 CHARACTERISTICS Alternate Data Stack Code or None Data
A15-A8
2-8, 39
O
A19/S6, A18/S5, A17/S4, A16/S3
35 36 37 38
O O O O
RD
32
O
READ: Read strobe indicates that the processor is performing a memory or I/O read cycle, depending on the state of the IO/M pin or S2. This signal is used to read devices which reside on the 80C88 local bus. RD is active LOW during T2, T3, Tw of any read cycle, and is guaranteed to remain HIGH in T2 until the 80C88 local bus has floated. This line is held at a high impedance logic one state during "hold acknowledge" or "grant sequence". READY: is the acknowledgment from the address memory or I/O device that it will complete the data transfer. The RDY signal from memory or I/O is synchronized by the 82C84A clock generator to from READY. This signal is active HIGH. The 80C88 READY input is not synchronized. Correct operation is not guaranteed if the set up and hold times are not met. INTERRUPT REQUEST: is a level triggered input which is sampled during the last clock cycle of each instruction to determine if the processor should enter into an interrupt acknowledge operation. A subroutine is vectored to via an interrupt vector lookup table located in system memory. It can be internally masked by software resetting the interrupt enable bit. INTR is internally synchronized. This signal is active HIGH. TEST: input is examined by the "wait for test" instruction. If the TEST input is LOW, execution continues, otherwise the processor waits in an "idle" state. This input is synchronized internally during each clock cycle on the leading edge of CLK. NONMASKABLE INTERRUPT: is an edge triggered input which causes a type 2 interrupt. A subroutine is vectored to via an interrupt vector lookup table located in system memory. NMI is not maskable internally by software. A transition from a LOW to HIGH initiates the interrupt at the end of the current instruction. This input is internally synchronized. RESET: cases the processor to immediately terminate its present activity. The signal must transition LOW to HIGH and remain active HIGH for at least four clock cycles. It restarts execution, as described in the instruction set description, when RESET returns LOW. RESET is internally synchronized. CLOCK: provides the basic timing for the processor and bus controller. It is asymmetric with a 33% duty cycle to provide optimized internal timing. VCC: is the +5V power supply pin. A 0.1F capacitor between pins 20 and 40 recommended for decoupling. GND: are the ground pins (both pins must be connected to system ground). A 0.1F capacitor between pins 1 and 20 is recommended for decoupling.
READY
22
I
INTR
18
I
TEST
23
I
NMI
17
I
RESET
21
I
CLK VCC GND MN/MX
19 40 1, 20 33`
I
I
MINIMUM/MAXIMUM: indicates the mode in which the processor is to operate. The two modes are discussed in the following sections.
3-4
80C88 Pin Description (Continued)
The following pin function descriptions are for 80C88 system in minimum mode (i.e., MN/MX = VCC). Only the pin functions which are unique to the minimum mode are described; all other pin functions are as described above. MINIMUM MODE SYSTEM
PIN NUMBER 28
SYMBOL IO/M
TYPE O
DESCRIPTION STATUS LINE: is an inverted maximum mode S2. It is used to distinguish a memory access from an I/O access. IO/M becomes valid in the T4 preceding a bus cycle and remains valid until the final T4 of the cycle (I/O = HIGH, M = LOW). IO/M is held to a high impedance logic one during local bus "hold acknowledge". Write: strobe indicates that the processor is performing a write memory or write I/O cycle, depending on the state of the IO/M signal. WR is active for T2, T3, and Tw of any write cycle. It is active LOW, and is held to high impedance logic one during local bus "hold acknowledge". INTA: is used as a read strobe for interrupt acknowledge cycles. It is active LOW during T2, T3 and Tw of each interrupt acknowledge cycle. Note that INTA is never floated. ADDRESS LATCH ENABLE: is provided by the processor to latch the address into the 82C82/82C83 address latch. It is a HIGH pulse active during clock low of T1 of any bus cycle. Note that ALE is never floated. DATA TRANSMIT/RECEIVE: is needed in a minimum system that desires to use an 82C86/82C87 data bus transceiver. It is used to control the direction of data flow through the transceiver. Logically, DT/R is equivalent to S1 in the maximum mode, and its timing is the same as for IO/M (T = HIGH, R = LOW). This signal is held to a high impedance logic one during local bus "hold acknowledge". DATA ENABLE: is provided as an output enable for the 82C86/82C87 in a minimum system which uses the transceiver. DEN is active LOW during each memory and I/O access, and for INTA cycles. For a read or INTA cycle, it is active from the middle of T2 until the middle of T4, while for a write cycle, it is active from the beginning of T2 until the middle of T4. DEN is held to high impedance logic one during local bus "hold acknowledge". HOLD: indicates that another master is requesting a local bus "hold". To be acknowledged, HOLD must be active HIGH. The processor receiving the "hold" request will issue HLDA (HIGH) as an acknowledgment, in the middle of a T4 or T1 clock cycle. Simultaneous with the issuance of HLDA the processor will float the local bus and control lines. After HOLD is detected as being LOW, the processor lowers HLDA, and when the processor needs to run another cycle, it will again drive the local bus and control lines. Hold is not an asynchronous input. External synchronization should be provided if the system cannot otherwise guarantee the set up time. STATUS LINE: is logically equivalent to S0 in the maximum mode. The combination of SS0, IO/M and DT/R allows the system to completely decode the current bus cycle status. SS0 is held to high impedance logic one during local bus "hold acknowledge". IO/M 1 1 1 1 0 0 0 0 DT/R 0 0 1 1 0 0 1 1 SS0 0 1 0 1 0 1 0 1 CHARACTERISTICS Interrupt Acknowledge Read I/O Port Write I/O Port Halt Code Access Read Memory Write Memory Passive
WR
29
O
INTA
24
O
ALE
25
O
DT/R
27
O
DEN
26
O
HOLD, HLDA
31 30
I O
SS0
34
O
3-5
80C88 Pin Description (Continued)
The following pin function descriptions are for 80C88 system in maximum mode (i.e., MN/MX = GND). Only the pin functions which are unique to the maximum mode are described; all other pin functions are as described above. MAXIMUM MODE SYSTEM
SYMBOL S0 S1 S2 PIN NUMBER 26 27 28 TYPE O O O DESCRIPTION STATUS: is active during clock high of T4, T1 and T2, and is returned to the passive state (1, 1, 1) during T3 or during Tw when READY is HIGH. This status is used by the 82C88 bus controller to generate all memory and I/O access control signals. Any change by S2, S1 or S0 during T4 is used to indicate the beginning of a bus cycle, and the return to the passive state in T3 or Tw is used to indicate the end of a bus cycle. These signals are held at a high impedance logic one state during "grant sequence". S2 0 0 0 0 1 1 1 1 RQ/GT0, RQ/GT1 31 30 I/O S1 0 0 1 1 0 0 1 1 S0 0 1 0 1 0 1 0 1 CHARACTERISTICS Interrupt Acknowledge Read I/O Port Write I/O Port Halt Code Access Read Memory Write Memory Passive
REQUEST/GRANT: pins are used by other local bus masters to force the processor to release the local bus at the end of the processor's current bus cycle. Each pin is bidirectional with RQ/GT0 having higher priority than RQ/GT1. RQ/GT has internal bus-hold high circuitry and, if unused, may be left unconnected. The request/grant sequence is as follows (see RQ/GT Timing Sequence): 1. A pulse of one CLK wide from another local bus master indicates a local bus request ("hold") to the 80C88 (pulse 1). 2. During a T4 or T1 clock cycle, a pulse one clock wide from the 80C88 to the requesting master (pulse 2), indicates that the 80C88 has allowed the local bus to float and that it will enter the "grant sequence" state at the next CLK. The CPUs bus interface unit is disconnected logically from the local bus during "grant sequence". 3. A pulse one CLK wide from the requesting master indicates to the 80C88 (pulse 3) that the "hold" request is about to end and that the 80C88 can reclaim the local bus at the next CLK. The CPU then enters T4 (or T1 if no bus cycles pending). Each master-master exchange of the local bus is a sequence of three pulses. There must be one idle CLK cycle after bus exchange. Pulses are active LOW. If the request is made while the CPU is performing a memory cycle, it will release the local bus during T4 of the cycle when all the following conjugations are met: 1. Request occurs on or before T2. 2. Current cycle is not the low bit of a word. 3. Current cycle is not the first acknowledge of an interrupt acknowledge sequence. 4. A locked instruction is not currently executing. If the local bus is idle when the request is made the two possible events will follow: 1. Local bus will be released during the next clock. 2. A memory cycle will start within 3 clocks. Now the four rules for a currently active memory cycle apply with condition number 1 already satisfied. LOCK: indicates that other system bus masters are not to gain control of the system bus while LOCK is active (LOW). The LOCK signal is activated by the "LOCK" prefix instruction and remains active until the completion of the next instruction. This signal is active LOW, and is held at a high impedance logic one state during "grant sequence". In Max Mode, LOCK is automatically generated during T2 of the first INTA cycle and removed during T2 of the second INTA cycle. QUEUE STATUS: provide status to allow external tracking of the internal 80C88 instruction queue. The queue status is valid during the CLK cycle after which the queue operation is performed. Note that the queue status never goes to a high impedance statue (floated). QS1 QS0 0 0 1 1 0 1 0 1 CHARACTERISTICS No Operation First Byte of Opcode from Queue Empty the Queue Subsequent Byte from Queue
LOCK
29
O
QS1, QS0
24, 25
O
-
34
O
Pin 34 is always a logic one in the maximum mode and is held at a high impedance logic one during a "grant sequence".
3-6
80C88 Functional Description
Static Operation All 80C88 circuitry is static in design. Internal registers, counters and latches are static and require not refresh as with dynamic circuit design. This eliminates the minimum operating frequency restriction placed on other microprocessors. The CMOS 80C88 can operate from DC to the specified upper frequency limit. The processor clock may be stopped in either state (high/low) and held there indefinitely. This type of operation is especially useful for system debug or power critical applications. The 80C88 can be single stepped using only the CPU clock. This state can be maintained as long as is necessary. Single step clock operation allows simple interface circuitry to provide critical information for start-up. Static design also allows very low frequency operation (as low as DC). In a power critical situation, this can provide extremely low power operation since 80C88 power dissipation is directly related to operation frequency. As the system frequency is reduced, so is the operating power until, at a DC input frequency, the power requirement is the 80C88 standby current. Internal Architecture The internal functions of the 80C88 processor are partitioned logically into two processing units. The first is the Bus Interface Unit (BIU) and the second is the Execution Unit (EU) as shown in the CPU block diagram. These units can interact directly but for the most part perform as separate asynchronous operational processors. The bus interface unit provides the functions related to instruction fetching and queuing, operand fetch and store, and address relocation. This unit also provides the basic bus control. The overlap of instruction pre-fetching provided by this unit serves to increase processor performance through improved bus bandwidth utilization. Up to 4 bytes of the instruction stream can be queued while waiting for decoding and execution. The instruction stream queuing mechanism allows the BIU to keep the memory utilized very efficiently. Whenever there is space for at least 1 byte in the queue, the BIU will attempt a byte fetch memory cycle. This greatly reduces "dead time": on the memory bus. The queue acts as a First-In-First-Out (FIFO) buffer, from which the EU extracts instruction bytes as required. If the queue is empty (following a branch instruction, for example), the first byte into the queue immediately becomes available to the EU. The execution unit receives pre-fetched instructions from the BIU queue and provides unrelocated operand addresses to the BIU. Memory operands are passed through the BIU for processing by the EU, which passes results to the BIU for storage. Memory Organization The processor provides a 20-bit address to memory which locates the byte being referenced. The memory is organized as a linear array of up to 1 million bytes, addressed as 00000(H) to FFFFF(H). The memory is logically divided into code, data, extra, and stack segments of up to 64K bytes each, with each segment falling on 16 byte boundaries. (See Figure 1).
7 0 FFFFFH
64K-BIT
CODE SEGMENT XXXXOH
STACK SEGMENT + OFFSET
SEGMENT REGISTER FILE CS SS DS ES EXTRA SEGMENT WORD LSB BYTE MSB DATA SEGMENT
00000H
FIGURE 14. MEMORY ORGANIZATION
All memory references are made relative to base addresses contained in high speed segment registers. The segment types were chosen based on the addressing needs of programs. The segment register to be selected is automatically chosen according to specific rules as shown in Table 1. All information in one segment type share the same logical attributes (e.g., code or data). By structuring memory into relocatable areas of similar characteristics and by automatically selecting segment registers, programs are shorter, faster, and more structured.
TABLE 6. MEMORY REFERENCE NEED Instructions Stack SEGMENT REGISTER USED CODE (CS) STACK (SS) SEGMENT SELECTION RULE Automatic with all instruction prefetch. All stack pushes and pops. Memory references relative to BP base register except data references. Data references when: relative to stack, destination of string operation, or explicitly overridden. Destination of string operations: Explicitly selected using a segment override.
Local Data
DATA (DS)
External Data (Global)
EXTRA (ES)
Word (16-bit) operands can be located on even or odd address boundaries. For address and data operands, the least significant byte of the word is stored in the lower valued address location and the most significant byte in the next higher address location.
3-7
80C88
The BIU will automatically execute two fetch or write cycles for 16-bit operands. Certain locations in memory are reserved for specific CPU operations. (See Figure 2). Locations from addresses FFFF0H through FFFFFH are reserved for operations including a jump to initial system initialization routine. Following RESET, the CPU will always begin execution at location FFFF0H where the jump must be located. Locations 00000H through 003FFH are reserved for interrupt operations. Each of the 256 possible interrupt service routines is accessed through its own pair of 16-bit pointers - segment address pointer and offset address pointer. The first pointer, used as the offset address, is loaded into the IP, and the second pointer, which designates the base address, is loaded into the CS. At this point program control is transferred to the interrupt routine. The pointer elements are assumed to have been stored at their respective places in reserved memory prior to the occurrence of interrupts. Minimum and Maximum Modes The requirements for supporting minimum and maximum 80C88 systems are sufficiently different that they cannot be done efficiently with 40 uniquely defined pins. Consequently, the 80C88 is equipped with a strap pin (MN/MX) which defines the system configuration. The definition of a certain subset of the pins changes, dependent on the condition of
FFFFFH FFFF0H
the strap pin. When the MN/MX pin is strapped to GND, the 80C88 defines pins 24 through 31 and 34 in maximum mode. When the MN/MX pins is strapped to VCC, the 80C88 generates bus control signals itself on pins 24 through 31 and 34. The minimum mode 80C88 can be used with either a muliplexed or demultiplexed bus. This architecture provides the 80C88 processing power in a highly integrated form. The demultiplexed mode requires one latch (for 64K addressability) or two latches (for a full megabyte of addressing). An 82C86 or 82C87 transceiver can also be used if data bus buffering is required. (See Figure 3). The 80C88 provides DEN and DT/R to control the transceiver, and ALE to latch the addresses. This configuration of the minimum mode provides the standard demultiplexed bus structure with heavy bus buffering and relaxed bus timing requirements. The maximum mode employs the 82C88 bus controller (See Figure 4). The 82C88 decode status lines S0, S1 and S2, and provides the system with all bus control signals. Moving the bus control to the 82C88 provides better source and sink current capability to the control lines, and frees the 80C88 pins for extended large system features. Hardware lock, queue status, and two request/grant interfaces are provided by the 80C88 in maximum mode. These features allow coprocessors in local bus and remote bus configurations.
RESET BOOTSTRAP PROGRAM JUMP
3FFH 3FCH AVAILABLE INTERRUPT POINTERS (224)
TYPE 255 POINTER (AVAILABLE)
084H 080H 07FH
TYPE 33 POINTER (AVAILABLE) TYPE 32 POINTER (AVAILABLE) TYPE 31 POINTER (AVAILABLE)
RESERVED INTERRUPT POINTERS (27)
014H 010H 00CH DEDICATED INTERRUPT POINTERS (5) 008H 004H 000H
TYPE 5 POINTER (RESERVED) TYPE 4 POINTER OVERFLOW TYPE 3 POINTER 1 BYTE INT INSTRUCTION TYPE 2 POINTER NON MASKABLE TYPE 1 POINTER SINGLE STEP TYPE 0 POINTER DIVIDE ERROR CS BASE ADDRESS IP OFFSET
16-BITS
FIGURE 15. RESERVED MEMORY LOCATIONS
3-8
80C88
VCC MN/MX CLK READY RESET VCC
82C84A/85 RES RDY CLOCK GENERATOR
IO/M
RD WR
GND
INTA 80C88 DT/R CPU DEN 1 GND ALE GND ADDR/DATA AD0-AD7 A8-A19 GND STB OE 82C82 LATCH (1, 2 OR 3) ADDRESS
VCC
C1 20 C2 40 C1 = C2 = 0.1F
VCC INTR
T OE 82C86 TRANSCEIVER DATA
EN 82C59A INTERRUPT CONTROL INT
OE HM-65162 CMOS PROM IR0-7 HS-6616 CMOS PROM
CS
RD WR
82CXX PERIPHERALS
FIGURE 16. DEMULTIPLEXED BUS CONFIGURATION
VCC MN/MX S0 S1 S2 GND CLK S0 MRDC MWTC NC
82C84A/85 RES RDY
CLK
READY RESET
GND 80C88 CPU 1 GND VCC C1 20 C2 40 C1 = C2 = 0.1F VCC INT AD0-AD7 A8-A19 GND GND ADDR/DATA
82C88 AMWC S1 IORC S2 IOWC DEN DT/R AIOWC ALE INTA
NC
STB OE 82C82 LATCH (1, 2 OR 3) ADDRESS
T OE 82C86 TRANSCEIVER DATA
OE 82C59A INTERRUPT CONTROL HM-65162 CMOS PROM IR0-7 HS-6616 CMOS PROM
CS
RD WR
82CXX PERIPHERALS
FIGURE 17. FULLY BUFFERED SYSTEM USING BUS CONTROLLER
3-9
80C88
Bus Operation The 80C88 address/data bus is broken into three parts: the lower eight address/data bits (AD0-AD7), the middle eight address bits (A8-A15), and the upper four address bits (A16A19). The address/data bits and the highest four address bits are time multiplexed. This technique provides the most efficient use of pins on the processor, permitting the use of standard 40 lead package. The middle eight address bits are not multiplexed, i.e., they remain valid throughout each bus cycle. In addition, the bus can be demultiplexed at the processor with a single address latch if a standard, nonmultiplexed bus is desired for the system. Each processor bus cycle consists of at least four CLK cycles. These are referred to as T1, T2, T3 and T4. (See Figure 5). The address is emitted from the processor during T1 and data transfer occurs on the bus during T3 and T4. T2 is used primarily for changing the direction of the bus during read operations. In the event that a "Not Ready" indication is given by the addressed device, "wait" states (TW) are inserted between T3 and T4. Each inserted "wait" state is of
(4 + NWAIT) = TCY T1 CLK GOES INACTIVE IN THE STATE JUST PRIOR TO T4 ALE T2 T3 TWAIT T4 T1 T2
the same duration as a CLK cycle. Periods can occur between 80C88 driven bus cycles. These are referred to as "idle" states (TI), or inactive CLK cycles. The processor uses these cycles for internal housekeeping. During T1 of any bus cycle, the ALE (Address latch enable) signal is emitted (by either the processor or the 82C88 bus controller, depending on the MN/MX strap). At the trailing edge of this pulse, a valid address and certain status information for the cycle may be latched. Status bits S0, S1, and S2 are used by the bus controller, in maximum mode, to identify the type of bus transaction according to Table 2. Status bits S3 through S6 are multiplexed with high order address bits and are therefore valid during T2 through T4. S3 and S4 indicate which segment register was used to this bus cycle in forming the address according to Table 3. S5 is a reflection of the PSW interrupt enable bit. S6 is always equal to 0.
(4 + NWAIT) = TCY T3 TWAIT T4
S2-S0
ADDR STATUS
A19-A16
S6-S3
A19-A16
S6-S3
ADDR
A15-A8
A15-A8
ADDR DATA
A7-A0
BUS RESERVED FOR DATA IN
D15-D0 VALID
A7-A0
DATA OUT (D7-D0)
RD, INTA READY READY WAIT DT/R WAIT READY
DEN MEMORY ACCESS TIME
WP
FIGURE 18. BASIC SYSTEM TIMING
3-10
80C88
TABLE 7. S2 0 0 0 0 1 1 1 1 S1 0 0 1 1 0 0 1 1 S0 0 1 0 1 0 1 0 1 CHARACTERISTICS Interrupt Acknowledge Read I/O Write I/O Halt Instruction Fetch Read Data from Memory Write Data to Memory Passive (No Bus Cycle) TABLE 8. S4 0 0 1 1 S3 0 1 0 1 CHARACTERISTICS Alternate Data (Extra Segment) Stack Code or None Data
OUTPUT DRIVER INPUT BUFFER
Bus Hold Circuitry To avoid high current conditions caused by floating inputs to CMOS devices and to eliminate the need for pull-up/down resistors, "bus-hold" circuitry has been used on 80C88 pins 2-16, 26-32 and 34-39 (see Figure 6A and 6B). These circuits maintain a valid logic state if no driving source is present (i.e., an unconnected pin or a driving source which goes to a high impedance state). To override the "bus hold" circuits, an external driver must be capable of supplying 400A minimum sink or source current at valid input voltage levels. Since this "bus hold" circuitry is active and not a "resistive" type element, the associated power supply current is negligible. Power dissipation is significantly reduced when compared to the use of passive pullup resistors.
BOND PAD EXTERNAL PIN
INPUT PROTECTION CIRCUITRY
I/O Addressing In the 80C88, I/O operations can address up to a maximum of 64K I/O registers. The I/O address appears in the same format as the memory address on bus lines A15-A0. The address lines A19-A16 are zero in I/O operations. The variable I/O instructions, which use register DX as a pointer, have full address capability, while the direct I/O instructions directly address one or two of the 256 I/O byte locations in page 0 of the I/O address space. I/O ports are addressed in the same manner as memory locations. Designers familiar with the 8085 or upgrading an 8085 design should note that the 8085 addresses I/O with an 8-bit address on both halves of the 16-bit address bus. The 80C88 uses a full 16-bit address on its lower 16 address lines.
FIGURE 19A. BUS HOLD CIRCUITRY PIN 2-16, 35-39
BOND PAD OUTPUT DRIVER INPUT BUFFER VCC P
EXTERNAL PIN
INPUT PROTECTION CIRCUITRY
FIGURE 19B. BUS HOLD CIRCUITRY PIN 26-32, 34
External Interface
Processor Reset and Initialization Processor initialization or start up is accomplished with activation (HIGH) of the RESET pin. The 80C88 RESET is required to be HIGH for greater than four clock cycles. The 80C88 will terminate operations on the high-going edge of RESET and will remain dormant as long as RESET is HIGH. The low-going transition of RESET triggers an internal reset sequence for approximately 7 clock cycles. After this interval the 80C88 operates normally, beginning with the instruction in absolute location FFFFOH (see Figure 2). The RESET input is internally synchronized to the processor clock. At initialization, the HIGH to LOW transition of RESET must occur no sooner than 50s after power up, to allow complete initialization of the 80C88. NMI will not be recognized if asserted prior to the second CLK cycle following the end of RESET.
Interrupt Operations Interrupt operations fall into two classes: software or hardware initiated. The software initiated interrupts and software aspects of hardware interrupts are specified in the instruction set description. Hardware interrupts can be classified as nonmaskable or maskable. Interrupts result in a transfer of control to a new program location. A 256 element table containing address pointers to the interrupt service program locations resides in absolute locations 0 through 3FFH (see Figure 2), which are reserved for this purpose. Each element in the table is 4 bytes in size and corresponds to an interrupt "type". An interrupting device supplies an 8-bit type number, during the interrupt acknowledge sequence, which is used to vector through the appropriate element to the new interrupt service program location.
3-11
80C88
Non-Maskable Interrupt (NMI) The processor provides a single non-maskable interrupt (NMI) pin which has higher priority than the maskable interrupt request (INTR) pin. A typical use would be to activate a power failure routine. The NMI is edge-triggered on a LOW to High transition. The activation of this pin causes a type 2 interrupt. NMI is required to have a duration in the HIGH state of greater than two clock cycles, but is not required to be synchronized to the clock. An high going transition of NMI is latched on-chip and will be serviced at the end of the current instruction or between whole moves (2 bytes in the case of word moves) of a block type instruction. Worst case response to NMI would be for multiply, divide, and variable shift instructions. There is no specification on the occurrence of the low-going edge; it may occur before, during, or after the servicing of NMI. Another high-going edge triggers another response if it occurs after the start of the NMI procedure. The signal must be free of logical spikes in general and be free of bounces on the low-going edge to avoid triggering extraneous responses. Maskable Interrupt (INTR) The 80C88 provides a singe interrupt request input (INTR) which can be masked internally by software with the resetting of the interrupt enable (IF) flag bit. The interrupt request signal is level triggered. It is internally synchronized during each clock cycle on the high-going edge of CLK. To be responded to, INTR must be present (HIGH) during the clock period preceding the end of the current instruction or the end of a whole move for a block type instruction. INTR may be removed anytime after the falling edge of the first INTA signal. During interrupt response sequence, further interrupts are disabled. The enable bit is reset as part of the response to any interrupt (INTR, NMI, software interrupt, or single step). The FLAGS register, which is automatically pushed onto the stack, reflects the state of the processor prior to the interrupt. The enable bit will be zero until the old FLAGS register is restored, unless specifically set by an instruction. During the response sequence (see Figure 7), the processor executes two successive (back-to-back) interrupt acknowledge cycles. The 80C88 emits to LOCK signal (maximum mode only) from T2 of the first bus cycle until T2 of the second. A local bus "hold" request will not be honored until the end of the second bus cycle. In the second bus cycle, a byte is fetched from the external interrupt system (e.g., 82C59A PIC) which identifies the source (type) of the interrupt. This byte is multiplied by four and used as a pointer into the interrupt vector lookup table. An INTR signal left HIGH will be continually responded to within the limitations of the enable bit and sample period. INTR may be removed anytime after the falling edge of the first INTA signal. The interrupt return instruction includes a flags pop which returns the status of the original interrupt enable bit when it restores the flags.
T1 ALE T2 T3 T4 T1 T2 T3 T4
LOCK
INTA
AD0AD7
TYPE VECTOR
FIGURE 20. INTERRUPT ACKNOWLEDGE SEQUENCE
Halt When a software HALT instruction is executed, the processor indicates that it is entering the HALT state in one of two ways, depending upon which mode is strapped. In minimum mode, the processor issues ALE, delayed by one clock cycle, to allow the system to latch the halt status. Halt status is available on IO/M, DT/R, and SS0. In maximum mode, the processor issues appropriate HALT status on S2, S1 and S0, and the 82C88 bus controller issues one ALE. The 80C88 will not leave the HALT state when a local bus hold is entered while in HALT. In this case, the processor reissues the HALT indicator at the end of the local bus hold. An interrupt request or RESET will force the 80C88 out of the HALT state. Read/Modify/Write (Semaphore) Operations Via LOCK The LOCK status information is provided by the processor when consecutive bus cycles are required during the execution of an instruction. This allows the processor to perform read/modify/write operations on memory (via the "exchange register with memory" instruction), without another system bus master receiving intervening memory cycles. This is useful in multiprocessor system configurations to accomplish "test and set lock" operations. The LOCK signal is activated (LOW) in the clock cycle following decoding of the LOCK prefix instruction. It is deactivated at the end of the last bus cycle of the instruction following the LOCK prefix. While LOCK is active, a request on a RQ/GT pin will be recorded, and then honored at the end of the LOCK. External Synchronization Via TEST As an alternative to interrupts, the 80C88 provides a single software-testable input pin (TEST). This input is utilized by executing a WAIT instruction. The single WAIT instruction is repeatedly executed until the TEST input goes active (LOW). The execution of WAIT does not consume bus cycles once the queue is full. If a local bus request occurs during WAIT execution, the 80C88 three-states all output drivers while inputs and I/O pins are held at valid logic levels by internal bus-hold circuits. If interrupts are enabled, the 80C88 will recognize interrupts and process them when it regains control of the bus.
3-12
80C88
Basic System Timing In minimum mode, the MN/MX pin is strapped to VCC and the processor emits bus control signals (RD, WR, IO/M, etc.) directly. In maximum mode, the MN/MX pin is strapped to GND and the processor emits coded status information which the 82C88 bus controller uses to generate MULTIBUSTM compatible bus control signals. System Timing - Minimum System The read cycle begins in T1 with the assertion of the address latch enable (ALE) signal (see Figure 5). The trailing (low going) edge of this signal is used to latch the address information, which is valid on the address data bus (ADO-AD7) at this time, into the 82C82/82C83 latch. Address lines A8 through A15 do not need to be latched because they remain valid throughout the bus cycle. From T1 to T4 the IO/M signal indicates a memory or I/O operation. At T2 the address is removed from the address data bus and the bus is held at the last valid logic state by internal bus-hold devices. The read control signal is also asserted at T2. The read (RD) signal causes the addressed device to enable its data bus drivers to the local bus. Some time later, valid data will be available on the bus and the addressed device will drive the READY line HIGH. When the processor returns the read signal to a HIGH level, the addressed device will again three-state its bus drivers. If a transceiver (82C86/82C87) is required to buffer the local bus, signals DT/R and DEN are provided by the 80C88. A write cycle also begins with the assertion of ALE and the emission of the address. The IO/M signal is again asserted to indicate a memory or I/O write operation. In T2, immediately following the address emission, the processor emits the data to be written into the addressed location. This data remains valid until at least the middle of T4. During T2, T3, and Tw, the processor asserts the write control signal. The write (WR) signal becomes active at the beginning of T2, as opposed to the read, which is delayed somewhat into T2 to provide time for output drivers to become inactive. The basic difference between the interrupt acknowledge cycle and a read cycle is that the interrupt acknowledge (INTA) signal is asserted in place of the read (RD) signal and the address bus is held at the last valid logic state by internal bus-hold devices (see Figure 6). In the second of two successive INTA cycles, a byte of information is read from the data bus, as supplied by the interrupt system logic (i.e., 82C59A priority interrupt controller). This byte identifies the source (type) of the interrupt. It is multiplied by four and used as a pointer into the interrupt vector lookup table, as described earlier. Bus Timing - Medium Complexity Systems For medium complexity systems, the MN/MX pin is connected to GND and the 82C88 bus controller is added to the system, as well as an 82C82/82C83 latch for latching the system address, and an 82C86/82C87 transceiver to allow for bus loading greater than the 80C88 is capable of handling (see Figure 8). Signals ALE, DEN, and DT/R are generated by the 82C88 instead of the processor in this configuration, although their timing remains relatively the same. The 80C88 status outputs (S2, S1 and S0) provide type of cycle information and become 82C88 inputs. This bus cycle information specifies read (code, data or I/O), write (data or I/O), interrupt acknowledge, or software halt. The 82C88 thus issues control signals specifying memory read or write, I/O read or write, or interrupt acknowledge. The 82C88 provides two types of write strobes, normal and advanced, to be applied as required. The normal write strobes have data valid at the leading edge of write. The advanced write strobes have the same timing as read strobes, and hence, data is not valid at the leading edge of write. The 82C86/82C87 transceiver receives the usual T and OE inputs from the 82C88 DT/R and DEN outputs. The pointer into the interrupt vector table, which is passed during the second INTA cycle, can derive from an 82C59A located on either the local bus or the system bus. If the master 82C59A priority interrupt controller is positioned on the local bus, the 82C86/82C87 transceiver must be disabled when reading from the master 82C59A during the interrupt acknowledge sequence and software "poll". The 80C88 Compared to the 80C86 The 80C88 CPU is a 8-bit processor designed around the 8086 internal structure. Most internal functions of the 80C88 are identical to the equivalent 80C86 functions. The 80C88 handles the external bus the same way the 80C86 does with the distinction of handling only 8-bits at a time. Sixteen-bit operands are fetched or written in two consecutive bus cycles. Both processors will appear identical to the software engineer, with the exception of execution time. The internal register structure is identical and all instructions have the same end result. Internally, there are three differences between the 80C88 and the 80C86. All changes are related to the 8-bit bus interface. * The queue length is 4 bytes in the 80C88, whereas the 80C86 queue contains 6 bytes, or three words. The queue was shortened to prevent overuse of the bus by the BIU when prefetching instructions. This was required because of the additional time necessary to fetch instructions 8-bits at a time. * To further optimize the queue, the prefetching algorithm was changed. The 80C88 BIU will fetch a new instruction to load into the queue each time there is a 1 byte space available in the queue. The 80C86 waits until a 2 byte space is available. * The internal execution time of the instruction set is affected by the 8-bit interface. All 16-bit fetches and writes from/to memory take an additional four clock cycles. The CPU is also limited by the speed of instruction fetches. This latter problem only occurs when a series of simple operations occur. When the more sophisticated instructions of the 80C88 are being used, the queue has time to fill the execution proceeds as fast as the execution unit will allow.
MULTIBUSTM is a patented Intel bus.
3-13
80C88
The 80C88 and 80C86 are completely software compatible by virtue of their identical execution units. Software that is system dependent may not be completely transferable, but software that is not system dependent will operate equally as well on an 80C88 or an 80C86. The hardware interface of the 80C88 contains the major differences between the two CPUs. The pin assignments are nearly identical, however, with the following functional changes: * A8-A15: These pins are only address outputs on the 80C88. These address lines are latched internally and remain valid throughout a bus cycle in a manner similar to the 8085 upper address lines.
T1 CLK
* BHE has no meaning on the 80C88 and has been eliminated. * SS0 provides the S0 status information in the minimum mode. This output occurs on pin 34 in minimum mode only. DT/R, IO/M and SS0 provide the complete bus status in minimum mode. * IO/M has been inverted to be compatible with the 8085 bus structure. * ALE is delayed by one clock cycle in the minimum mode when entering HALT, to allow the status to be latched with ALE.
T2
T3
T4
QS1, QS0 80C88 S2, S1, S0
A19/S6 - A16/S3
A19 - A16
S6 - S3
ALE
80C88
RDY
82C84
READY
80C88
AD7 - AD0
DATA OUT
A7-A0
DATA IN
80C88
A15 - A8
A15 - A8
RD
DT/R
80C88
MRDC
DEN
FIGURE 21. MEDIUM COMPLEXITY SYSTEM TIMING
3-14
80C88
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0V Input, Output or I/O Voltage . . . . . . . . . . . GND -0.5V to VCC +0.5V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Information
Thermal Resistance (Typical) JA (oC/W) JC (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . 50 PLCC Package . . . . . . . . . . . . . . . . . . 46 SBDIP Package . . . . . . . . . . . . . . . . . . 30 N/A CLCC Package . . . . . . . . . . . . . . . . . . 40 N/A Maximum Junction Temperature Ceramic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150oC Storage Temperature Range . . . . . . . . . . . . . . . . . .-65oC to +150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300oC (Lead tips only for surface mount packages)
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V M80C88-2 Only. . . . . . . . . . . . . . . . . . . . . . . . . +4.75V to +5.25V Operating Temperature Range C80C88/-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to +70oC I80C88/-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC M80C88/-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9750 Gates
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
DC Electrical Specifications
VCC = 5.0V, 10%; VCC = 5.0V, 10%; VCC = 5.0V, 10%; VCC = 5.0V, 5%;
TA = 0oC to +70oC (C80C88, C80C88-2) TA = -40oC to +85oC (l80C88, I80C88-2) TA = -55oC to +125oC (M80C88) TA = -55oC to +125oC (M80C88-2) MIN 2.0 2.2 VCC -0.8 3.0 VCC -0.4 -1.0 -40 40 MAX 0.8 0.8 0.4 1.0 -400 400 -10.0 500 10 UNITS V V V V V V V V A A A A A mA/MHz lOH = -2.5mA lOH = -100A lOL = +2.5mA VIN = 0V or VCC Pins 17-19, 21-23, 33 VIN = - 3.0V (Note 1) VIN = - 0.8V (Note 2) VOUT = 0V (Note 5) VCC = 5.5V (Note 3) FREQ = Max, VIN = VCC or GND, Outputs Open TEST CONDITION C80C88, I80C88 (Note 4) M80C88 (Note 4)
SYMBOL VlH VIL VIHC VILC VOH VOL II lBHH lBHL IO ICCSB ICCOP NOTES: Logical One Input Voltage
PARAMETER
Logical Zero Input Voltage CLK Logical One Input Voltage CLK Logical Zero Input Voltage Output High Voltage Output Low Voltage Input Leakage Current Input Current-Bus Hold High Input Current-Bus Hold Low Output Leakage Current Standby Power Supply Current Operating Power Supply Current
1. lBHH should be measured after raising VIN to VCC and then lowering to 3.0V on the following pins 2-16, 26-32, 34-39. 2. IBHL should be measured after lowering VIN to GND and then raising to 0.8V on the following pins: 2-16, 35-39. 3. lCCSB tested during clock high time after HALT instruction executed. VIN = VCC or GND, VCC = 5.5V, Outputs unloaded. 4. MN/MX is a strap option and should be held to VCC or GND. 5. IO should be measured by putting the pin in a high impedance state and then driving VOUT to GND on the following pins: 26-29 and 32.
Capacitance
SYMBOL CIN COUT CI/O
TA = 25oC PARAMETER TYPICAL 25 25 25 UNITS pF pF pF TEST CONDITIONS FREQ = 1MHz. All measurements are referenced to device GND FREQ = 1MHz. All measurements are referenced to device GND FREQ = 1MHz. All measurements are referenced to device GND
Input Capacitance Output Capacitance I/O Capacitance
3-15
80C88
AC Electrical Specifications
VCC = 5.0V 10%; VCC = 5.0V 100%; VCC = 5.0V 100%; VCC = 5.0V 5%; TA = 0oC to +70oC (C80C88, C80C88-2) TA = -40oC to +85oC (I80C88, I80C88-2) TA = -55oC to +125oC (M80C88) TA = -55oC to +125oC (M80C88-2)
MINIMUM COMPLEXITY SYSTEM 80C88 SYMBOL TIMING REQUIREMENTS (1) (2) (3) (4) (5) (6) (7) (8) TCLCL TCLCH TCHCL TCH1CH2 TCL2CL1 TDVCL TCLDX1 TR1VCL CLK Cycle Period CLK Low Time CLK High Time CLK Rise Time CLK FaIl Time Data In Setup Time Data In Hold Time RDY Setup Time into 82C84A (Notes 6, 7) RDY Hold Time into 82C84A (Notes 6, 7) READY Setup Time into 80C88 READY Hold Time into 80C88 READY Inactive to CLK (Note 8) HOLD Setup Time lNTR, NMI, TEST Setup Time (Note 7) Input Rise Time (Except CLK) Input FaIl Time (Except CLK) 200 118 69 30 10 35 10 10 125 68 44 20 10 35 10 10 ns ns ns ns ns ns ns ns From 1.0V to 3.5V From 3.5V to 1.0V PARAMETER MIN MAX 80C88-2 MIN MAX UNITS TEST CONDITIONS
(9)
TCLR1X
0
-
0
-
ns
(10) (11) (12) (13) (14)
TRYHCH TCHRYX TRYLCL THVCH TINVCH
118 30 -8 35 30
-
68 20 -8 20 15
-
ns ns ns
ns
ns
(15) (16)
TILIH TIHIL
-
15 15
-
15 15
ns ns
From 0.8V to 2.0V From 2.0V to 0.8V
TIMING RESPONSES (17) (18) (19) (20) (21) (22) (23) (24) TCLAV TCLAX TCLAZ TCHSZ TCHSV TLHLL TCLLH TCHLL Address Valid Delay Address Hold Time Address Float Delay Status Float Delay Status Active Delay ALE Width ALE Active Delay ALE Inactive Delay 10 10 TCLAX 10 TCLCH-20 110 80 80 110 80 85 10 10 TCLAX 10 TCLCH-10 60 50 50 60 50 55 ns ns ns ns ns ns ns ns CL = 100pF CL = 100pF CL = 100pF CL = 100pF CL = 100pF CL = 100pF CL = 100pF CL = 100pF
3-16
80C88
AC Electrical Specifications
VCC = 5.0V 10%; VCC = 5.0V 100%; VCC = 5.0V 100%; VCC = 5.0V 5%; TA = 0oC to +70oC (C80C88, C80C88-2) TA = -40oC to +85oC (I80C88, I80C88-2) TA = -55oC to +125oC (M80C88) TA = -55oC to +125oC (M80C88-2) (Continued)
MINIMUM COMPLEXITY SYSTEM 80C88 SYMBOL (25) (26) (27) (28) (29) (30) (31) (32) (33) (34) (35) (36) (37) (38) (39) (40) (41) NOTES: 6. Signal at 82C84A shown for reference only. 7. Setup requirement for asynchronous signal only to guarantee recognition at next CLK. 8. Applies only to T2 state (8ns into T3). TLLAX TCLDV TCLDX2 TWHDX TCVCTV TCHCTV TCVCTX TAZRL TCLRL TCLRH TRHAV TCLHAV TRLRH TWLWH TAVAL TOLOH TOHOL PARAMETER Address Hold Time to ALE Inactive Data Valid Delay Data Hold Time Data Hold Time After WR Control Active Delay 1 Control Active Delay 2 Control Inactive Delay Address Float to READ Active RD Active Delay RD Inactive Delay RD Inactive to Next Address Active HLDA Valid Delay RD Width WR Width Address Valid to ALE Low Output Rise Time Output Fall Time MIN TCHCL-10 10 10 TCLCL-30 10 10 10 0 10 10 TCLCL-45 10 2TCLCL-75 2TCLCL-60 TCLCH-60 MAX 110 110 110 110 165 150 160 15 15 80C88-2 MIN TCHCL-10 10 10 TCLCL-30 10 10 10 0 10 10 TCLCL-40 10 2TCLCL-50 2TCLCL-40 TCLCH-40 MAX 60 70 60 70 100 80 100 15 15 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns TEST CONDITIONS CL = 100pF CL = 100pF CL = 100pF CL = 100pF CL = 100pF CL = 100pF CL = 100pF CL = 100pF CL = 100pF CL = 100pF CL = 100pF CL = 100pF CL = 100pF CL = 100pF CL = 100pF From 0.8V to 2.0V From 2.0V to 0.8V
3-17
80C88 Waveforms
T1 (1) TCLCL CLK (82C84A OUTPUT) (3) (30) TCHCTV IO/M, SSO (17) TCLAV A15-A8 A15-A8 (FLOAT DURING INTA) TCH1CH2 (4) TCHCL (2) TCLCH TCHCTV (30) T2 T3 TW (5) TCL2CL1 T4
(17) TCLAV A19/S6-A16/S3 (23) TCLLH ALE
(26) TCLDV (18) TCLAX A19-A16 TLHLL (22) (24) TCHLL TR1VCL (8) VIH VIL (12) TRYLCL TCLR1X (9) TLLAX (25) S6-S3
(17) TCLAV
RDY (82C84A INPUT) SEE NOTE 9, 10
TAVAL (39)
READY (80C88 INPUT)
(11) TCHRYX (10) TRYHCH (16) TDVCL DATA IN (34) TCLRH TRHAV (35)
(19) TCLAZ AD7-AD0 AD7-AD0 (32) TAZRL RD READ CYCLE (WR, INTA = VOH) DT/R (29) TCVCTV DEN (30) TCHCTV TCLRL (33)
(7) TCLDX1
TRLRH (37)
(30) TCHCTV
TCVCTX (31)
FIGURE 22. BUS TIMING - MINIMUM MODE SYSTEM NOTES: 9. RDY is sampled near the end of T2, T3, TW to determine if TW machine states are to be inserted. 10. Signals at 82C84A are shown for reference only.
3-18
80C88 Waveforms
(Continued)
T1 (4) TCH1CH2 CLK (82C84A OUTPUT) (17) TCLAV AD7-AD0 TCVCTV WRITE CYCLE DEN (29) TCVCTV WR (19) TCLAZ AD7-AD0 TCHCTV (30) INTA CYCLE (NOTE 11) RD, WR = VOH DT/R (29) TCVCTV INTA (29) TCVCTV DEN (26) TCLDV TCLAX AD7-AD0 (29)
T2
T3 (5) TCL2CL1
TW
T4
TW (27) TCLDX2 DATA OUT TWHDX (31) TCVCTX (28)
(18)
(38) TWLWH TCVCTX TDVCL (31) (6) TCLDX1 (7) POINTER TCHCTV (30)
TCVCTX (31)
SOFTWARE HALT DEN, RD, WR, INTA = VOH AD7-AD0 TCLAV (17) ALE TCHCTV (30)
INVALID ADDRESS
SOFTWARE HALT TCHLL (24)
TCLLH (23)
IO/M DT/R SSO
TCVCTX (31)
FIGURE 23. BUS TIMING - MINIMUM MODE SYSTEM (Continued) NOTES: 11. Two INTA cycles run back-to-back. The 80C88 local ADDR/DATA bus is floating during both INTA cycles. Control signals are shown for the second INTA cycle. 12. Signals at 82C84A are shown for reference only.
3-19
80C88
AC Electrical Specifications
VCC = 5.0V 10%; VCC = 5.0V 10%; VCC = 5.0V 10%; VCC = 5.0V 5%; TA = 0oC to +70oC (C80C88, C80C88-2) TA = -40oC to +85oC (I80C88, I80C88-2) TA = -55oC to +125oC (M80C88) TA = -55oC to +125oC (M80C88-2) 80C88 SYMBOL TIMING REQUIREMENTS (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) (15) (16) (17) TCLCL TCLCH TCHCL TCH1CH2 TCL2CL1 TDVCL TCLDX1 TR1VCL TCLR1X TRYHCH TCHRYX TRYLCL TlNVCH TGVCH TCHGX TILlH TIHIL CLK Cycle Period CLK Low Time CLK High Time CLK Rise Time CLK Fall Time Data in Setup Time Data In Hold Time RDY Setup Time into 82C84 (Notes 13, 14) RDY Hold Time into 82C84 (Notes 13, 14) READY Setup Time into 80C88 READY Hold Time into 80C88 READY Inactive to CLK (Note 15) Setup Time for Recognition (lNTR, NMl, TEST) (Note 14) RQ/GT Setup Time RQ Hold Time into 80C88 (Note 16) Input Rise Time (Except CLK) Input Fall Time (Except CLK) 200 118 69 30 10 35 0 118 30 -8 30 30 40 10 10 TCHCL+ 10 15 15 125 68 44 20 10 35 0 68 20 -8 15 15 30 10 10 TCHCL+ 10 15 15 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns From 0.8V to 2.0V From 2.0V to 0.8V From 1.0V to 3.5V From 3.5V to 1.0V PARAMETER MIN MAX 80C88-2 MIN MAX UNITS TEST CONDITIONS
MAX MODE SYSTEM (USING 82C88 BUS CONTROLLER)
TIMING RESPONSES (18) (19) (20) (21) (22) (23) (24) (25) (26) (27) (28) (29) (30) (31) TCLML TCLMH TRYHSH TCHSV TCLSH TCLAV TCLAX TCLAZ TCHSZ TSVLH TSVMCH TCLLH TCLMCH TCHLL Command Active Delay (Note 13) Command Inactive (Note 13) READY Active to Status Passive (Notes 15, 17) Status Active Delay Status Inactive Delay (Note 17) Address Valid Delay Address Hold Time Address Float Delay Status Float Delay Status Valid to ALE High (Note 13) Status Valid to MCE High (Note 13) CLK Low to ALE Valid (Note 13) CLK Low to MCE High (Note 13) ALE Inactive Delay (Note 13) 5 5 10 10 10 10 TCLAX 4 35 35 110 110 130 110 80 80 20 30 20 25 18 5 5 10 10 10 10 TCLAX 4 35 35 65 60 70 60 50 50 20 30 20 25 18 ns ns ns ns ns ns ns ns ns ns ns ns ns ns CL = 100pF for all 80C88 outputs in addition to internal loads.
3-20
80C88
AC Electrical Specifications
VCC = 5.0V 10%; VCC = 5.0V 10%; VCC = 5.0V 10%; VCC = 5.0V 5%; TA = 0oC to +70oC (C80C88, C80C88-2) TA = -40oC to +85oC (I80C88, I80C88-2) TA = -55oC to +125oC (M80C88) TA = -55oC to +125oC (M80C88-2) (Continued) 80C88 SYMBOL (32) (33) (34) (35) (36) (37) (38) (39) (40) (41) (42) (43) (44) (45) (46) (47) NOTES: 13. Signal at 82C84A or 82C88 shown for reference only. 14. Setup requirement for asynchronous signal only to guarantee recognition at next CLK. 15. Applies only to T2 state (8ns into T3). 16. The 80C88 actively pulls the RQ/GT pin to a logic one on the following clock low time. 17. Status lines return to their inactive (logic one) state after CLK goes low and READY goes high. TCLMCL TCLDV TCLDX2 TCVNV TCVNX TAZRL TCLRL TCLRH TRHAV TCHDTL TCHDTH TCLGL TCLGH TRLRH TOLOH TOHOL PARAMETER MCE Inactive Delay (Note 13) Data Valid Delay Data Hold Time Control Active Delay (Note 13) Control Inactive Delay (Note 13) Address Float to Read Active RD Active Delay RD Inactive Delay RD Inactive to Next Address Active Direction Control Active Delay (Note 13) Direction Control Inactive Delay (Note 1) GT Active Delay GT Inactive Delay RD Width Output Rise Time Output Fall Time MIN 10 10 5 10 0 10 10 TCLCL -45 0 0 2TCLC L -75 MAX 15 110 45 45 165 150 50 30 85 85 15 15 80C88-2 MIN 10 10 5 10 0 10 10 TCLCL -40 0 0 2TCLC L -50 MAX 15 60 45 45 100 80 50 30 50 50 15 15 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns From 0.8V to 2.0V From 2.0V to 0.8V CL = 100pF for all 80C88 outputs in addition to internal loads. TEST CONDITIONS
MAX MODE SYSTEM (USING 82C88 BUS CONTROLLER)
3-21
80C88 Waveforms
T1 (1) TCLCL CLK (23) TCLAV QS0, QS1 (21) TCHSV S2, S1, S0 (EXCEPT HALT) A15-A8 (23) TCLAV A19/S6-A16/S3 TSVLH (27) ALE (82C88 OUTPUT) NOTES 18, 19 RDY (82C84 INPUT) TCLR1X (12) TRYLCL (11) TCHRYX (9) TCLLH (29) TR1VCL (8) TCLDV TCLAX A19-A16 TCHLL (31) (33) (24) S6-S3 A15-A8 (23) (22) TCLSH (SEE NOTE 20) TCHCL (3) TCLCH (2) T2 (4) TCH1CH2 T3 (5) TCL2CL1 T4
TW
TCLAV
READY 80C86 INPUT)
(24) TCLAX
TRYHSH (20) (10) TRYHCH
READ CYCLE AD7-AD0
TCLAV
(23)
(25) TCLAZ AD7-AD0 (37) TAZRL
(6) TDVCL DATA IN (39) TCLRH
(7) TCLDX1
TRHAV
(40) (42) TCHDTH
RD (41) TCHDTL TCLRL (38) TCLML 82C88 OUTPUTS SEE NOTES 19, 21 MRDC OR IORC (35) TCVNV DEN TCVNX (36) (18) TRLRH (45)
DT/R
TCLMH
(19)
FIGURE 24. BUS TIMING - MAXIMUM MODE (USING 82C88) NOTES: 18. RDY is sampled near the end of T2, T3, TW to determine if TW machine states are to be inserted. 19. Signals at 82C84A or 82C88 are shown for reference only. 20. Status inactive in state just prior to T4. 21. The issuance of the 82C88 command and control signals (MRDC, MWTC, AMWC, IORC, IOWC, AIOWC, INTA, and DEN) lags the active high 82C88 CEN.
3-22
80C88 Waveforms
(Continued)
T1 CLK TCHSV (21) S2, S1, S0 (EXCEPT HALT) TCLDV TCLAX (33) (24) (22) DATA TCVNV (35) DEN 82C88 OUTPUTS SEE NOTES 22, 23 (18) TCLML AMWC OR AIOWC (18)TCLML MWTC OR IOWC INTA CYCLE A15-A8 (SEE NOTES 25, 26) (25) TCLAZ AD7-AD0 (32) RESERVED FOR CASCADE ADDR (6) TDVCL POINTER TCLMCL (28) TSVMCH MCE/PDEN (30) TCLMCH DT/R 82C88 OUTPUTS SEE NOTES 22, 23, 25 (41) TCHDTL (42) TCLDX1 (7) TCLMH (19) TCLMH (19) TCVNX (36) (SEE NOTE 24) TCLDX2 (34) T2 T3 T4
TW
WRITE CYCLE AD7-AD0
TCLAV (23)
TCLSH
TCHDTH
(18) TCLML INTA (19) TCLMH
TCVNV (35) DEN SOFTWARE HALT - RD, MRDC, IORC, MWTC, AMWC, IOWC, AIOWC, INTA, S0, S1 = VOH AD7-AD0 A15-A8 TCLAV (23) S2, S1, S0 TCHSV (21) TCLSH (22) INVALID ADDRESS
TCVNX (36)
FIGURE 25. BUS TIMING - MAXIMUM MODE SYSTEM (USING 82C88) (Continued) NOTES: 22. Signals at 82C84A or 82C86 are shown for reference only. 23. The issuance of the 82C88 command and control signals (MRDC, MWTC, AMWC, IORC, IOWC, AIOWC, INTA and DEN) lags the active high 82C88 CEN. 24. Status inactive in state just prior to T4. 25. Cascade address is valid between first and second INTA cycles. 26. Two INTA cycles run back-to-back. The 80C88 local ADDR/DATA bus is floating during both INTA cycles. Control for pointer address is shown for second INTA cycle.
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80C88 Waveforms
(Continued)
ANY CLK CYCLE CLK TCLGH (44) (1) TCLCL TGVCH (14) TCHGX (15) TCLGL (43) PULSE 2 80C88 GT TCLGH (44) > 0-CLK CYCLES
RQ/GT PREVIOUS GRANT AD7-AD0 80C88
PULSE 1 COPROCESSOR RQ
TCLAZ (25)
PULSE 3 COPROCESSOR RELEASE COPROCESSOR TCHSV (21) (SEE NOTE)
TCHSZ (26) RD, LOCK A19/S6-A16/S3 S2, S1, S0
FIGURE 26. REQUEST/GRANT SEQUENCE TIMING (MAXIMUM MODE ONLY) NOTE: The coprocessor may not drive the busses outside the region shown without risking contention.
1CLK CYCLE CLK THVCH (13) HOLD
1 OR 2 CYCLES
THVCH (13) (SEE NOTE) TCLHAV (36) TCLHAV (36)
HLDA TCLAZ (19) A15-A8 AD7-AD0 TCHSZ (20) A19/S6-A16/S3 RD, WR, I/O/M, DT/R, DEN, SSO TCHSV (21) 80C88 COPROCESSOR 80C88
FIGURE 27. HOLD/HOLD ACKNOWLEDGE TIMING (MINIMUM MODE ONLY) NOTE: Setup requirements for asynchronous signals only to guarantee recognition at next CLK.
CLK ANY CLK CYCLE (13) TINVCH (SEE NOTE) SIGNAL LOCK CLK TCLAV (23)
ANY CLK CYCLE
NMI INTR TEST
TCLAV (23)
FIGURE 28. ASYNCHRONOUS SIGNAL RECOGNITION NOTE: Setup requirements for asynchronous signals only to guarantee recognition at next CLK.
FIGURE 29. BUS LOCK SIGNAL TIMING (MAXIMUM MODE ONLY)
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80C88 Waveforms
(Continued)
50s VCC
CLK (7) TCLDX1 (6) TDVCL RESET 4 CLK CYCLES
FIGURE 30. RESET TIMING
AC Test Circuit
OUTPUT FROM DEVICE UNDER TEST CL (NOTE) TEST POINT
AC Testing Input, Output Waveform
INPUT VIH + 20% VIH 1.5V VIL - 50% VIL 1.5V OUTPUT VOH VOL
NOTE: Includes stay and jig capacitance.
AC Testing: All input signals (other than CLK) must switch between VILMAX -50% VIL and VIHMIN +20% VIH. CLK must switch between 0.4V and VCC -0.4V. Input rise and fall times are driven at 1ns/V.
Burn-In Circuits
MD80C88 (CERDIP)
C GND GND VCL GND GND VCL GND GND GND VCL VCL VCL OPEN OPEN OPEN OPEN GND GND F0 GND RC RIO RIO RIO RIO RIO RIO RIO RIO RIO RIO RIO 1 GND 2 A14 3 A13 4 A12 5 A11 6 A10 7 A9 8 A8 9 AD7 10 AD6 11 AD5 12 AD4 13 AD3 14 AD2 15 AD1 16 AD0 17 NMI 18 INTR 19 CLK 20 GND VCC 40 A15 39 A16 38 A17 37 A18 36 A19 35 BHE 34 MX 33 RD 32 RQ0 31 RQ1 30 LOCK 29 S2 28 S1 27 S0 26 QS0 25 QS2 24 TEST 23 READY 22 RESET 21 RI RI RO RI RO RO RO RO RO RO RO VCL VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 GND VCL NODE A FROM PROGRAM CARD GND VCC VCL VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 GND VIL VCL
RIO RO RO RO RO RO
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80C88 Burn-In Circuits
(Continued) MR80C88 (CLCC)
C RIO RIO RIO RIO RIO RO RO RO VCC VCL
RIO RIO RIO RIO RIO RIO RIO
6 7 8 9 10 11 12 13 14 15 16 17
5
4
3
2
1 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 RO RO RO RI RI RO RO RO RO
18 19 20 21 22 23 24 25 26 27 28
RO
RC
RI
RI
RO
VCC/2 GND F0 A (FROM PROGRAM CARD)
NOTES: 1. VCC = 5.5V 0.5V, GND = 0V. 2. Input voltage limits (except clock): VIL (Maximum) = 0.4V VIH (Minimum) = 2.6V, VIH (Clock) = VCC - 0.4V) minimum. 3. VCC/2 is external supply set to 2.7V 10%. 4. VCL is generated on program card (VCC - 0.65V). 5. Pins 13 - 16 input sequenced instructions from internal hold devices, (DIP Only). 6. F0 = 100kHz 10%. 7. Node A = a 40s pulse every 2.56ms.
COMPONENTS: 1. RI = 10k 5%, 1/4W 2. RO = 1.2k 5%, 1/4W 3. RIO = 2.7k 5%, 1/4W 4. RC = 1k 5%, 1/4W 5. C = 0.01F (Minimum)
3-26
80C88 Die Characteristics
DIE DIMENSIONS: 249.2 x 290.9 x 19 1mils METALLIZATION: Type: Silicon - Aluminum Thickness: 11kA 2kA GLASSIVATION: Type: SiO2 Thickness: 8kA 1kA WORST CASE CURRENT DENSITY: 1.5 x 105 A/cm2
Metallization Mask Layout
80C88
A11 A12 A13 A14 GND VCC A15 A16/S3 A17/S4 A18/S5
A19/S6 A10 A9
SSO MN/MX
A8 AD7 RD
HOLD AD6 AD5 HLDA AD4 AD3 WR
AD2 AD1
IO/M
DT/R
AD0 NMI INTR CLK GND RESET READY TEST INTA ALE DEN
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80C88 Instruction Set Summary
INSTRUCTION CODE MNEMONIC AND DESCRIPTION DATA TRANSFER MOV = MOVE: Register/Memory to/from Register Immediate to Register/Memory Immediate to Register Memory to Accumulator Accumulator to Memory Register/Memory to Segment Register Segment Register to Register/Memory PUSH = Push: Register/Memory Register Segment Register POP = Pop: Register/Memory Register Segment Register XCHG = Exchange: Register/Memory with Register Register with Accumulator IN = Input from: Fixed Port Variable Port OUT = Output to: Fixed Port Variable Port XLAT = Translate Byte to AL LEA = Load EA to Register2 LDS = Load Pointer to DS LES = Load Pointer to ES LAHF = Load AH with Flags SAHF = Store AH into Flags PUSHF = Push Flags POPF = Pop Flags ARITHMETIC ADD = Add: Register/Memory with Register to Either Immediate to Register/Memory Immediate to Accumulator ADC = Add with Carry: Register/Memory with Register to Either 000100dw mod reg r/m 000000dw 100000sw 0000010w mod reg r/m mod 0 0 0 r/m data data data if w = 1 data if s:w = 01 1110011w 1110111w 11010111 10001101 11000101 11000100 10011111 10011110 10011100 10011101 mod reg r/m mod reg r/m mod reg r/m port 1110010w 1110110w port 1000011w 1 0 0 1 0 reg mod reg r/m 10001111 0 1 0 1 1 reg 0 0 0 reg 1 1 1 mod 0 0 0 r/m 11111111 0 1 0 1 0 reg 0 0 0 reg 1 1 0 mod 1 1 0 r/m 100010dw 1100011w 1 0 1 1 w reg 1010000w 1010001w 10001110 10001100 mod reg r/m mod 0 0 0 r/m data addr-low addr-low mod 0 reg r/m mod 0 reg r/m data data if w 1 addr-high addr-high data if w 1 76543210 76543210 76543210 76543210
3-28
80C88 Instruction Set Summary
(Continued) INSTRUCTION CODE MNEMONIC AND DESCRIPTION Immediate to Register/Memory Immediate to Accumulator INC = Increment: Register/Memory Register AAA = ASCll Adjust for Add DAA = Decimal Adjust for Add SUB = Subtract: Register/Memory and Register to Either Immediate from Register/Memory Immediate from Accumulator SBB = Subtract with Borrow Register/Memory and Register to Either Immediate from Register/Memory Immediate from Accumulator DEC = Decrement: Register/Memory Register NEG = Change Sign CMP = Compare: Register/Memory and Register Immediate with Register/Memory Immediate with Accumulator AAS = ASCll Adjust for Subtract DAS = Decimal Adjust for Subtract MUL = Multiply (Unsigned) IMUL = Integer Multiply (Signed) AAM = ASCll Adjust for Multiply DlV = Divide (Unsigned) IDlV = Integer Divide (Signed) AAD = ASClI Adjust for Divide CBW = Convert Byte to Word CWD = Convert Word to Double Word LOGIC NOT = Invert SHL/SAL = Shift Logical/Arithmetic Left SHR = Shift Logical Right SAR = Shift Arithmetic Right ROL = Rotate Left ROR = Rotate Right RCL = Rotate Through Carry Flag Left 1111011w 110100vw 110100vw 110100vw 110100vw 110100vw 110100vw mod 0 1 0 r/m mod 1 0 0 r/m mod 1 0 1 r/m mod 1 1 1 r/m mod 0 0 0 r/m mod 0 0 1 r/m mod 0 1 0 r/m 001110dw 100000sw 0011110w 00111111 00101111 1111011w 1111011w 11010100 1111011w 1111011w 11010101 10011000 10011001 mod 1 0 0 r/m mod 1 0 1 r/m 00001010 mod 1 1 0 r/m mod 1 1 1 r/m 00001010 mod reg r/m mod 1 1 1 r/m data data data if w = 1 data if s:w = 01 1111111w 0 1 0 0 1 reg 1111011w mod 0 1 1 r/m mod 0 0 1 r/m 000110dw 100000sw 0001110w mod reg r/m mod 0 1 1 r/m data data data if w = 1 data if s:w = 01 001010dw 100000sw 0010110w mod reg r/m mod 1 0 1 r/m data data data if w = 1 data if s:w = 01 1111111w 0 1 0 0 0 reg 00110111 00100111 mod 0 0 0 r/m 76543210 100000sw 0001010w 76543210 mod 0 1 0 r/m data 76543210 data data if w = 1 76543210 data if s:w = 01
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80C88 Instruction Set Summary
(Continued) INSTRUCTION CODE MNEMONIC AND DESCRIPTION RCR = Rotate Through Carry Right AND = And: Reg./Memory and Register to Either Immediate to Register/Memory Immediate to Accumulator TEST = And Function to Flags, No Result: Register/Memory and Register Immediate Data and Register/Memory Immediate Data and Accumulator OR = Or: Register/Memory and Register to Either Immediate to Register/Memory Immediate to Accumulator XOR = Exclusive or: Register/Memory and Register to Either Immediate to Register/Memory Immediate to Accumulator STRING MANIPULATION REP = Repeat MOVS = Move Byte/Word CMPS = Compare Byte/Word SCAS = Scan Byte/Word LODS = Load Byte/Word to AL/AX STOS = Stor Byte/Word from AL/A CONTROL TRANSFER CALL = Call: Direct Within Segment Indirect Within Segment Direct Intersegment 11101000 11111111 10011010 disp-low mod 0 1 0 r/m offset-low seg-low Indirect Intersegment JMP = Unconditional Jump: Direct Within Segment Direct Within Segment-Short Indirect Within Segment Direct Intersegment 11101001 11101011 11111111 11101010 disp-low disp mod 1 0 0 r/m offset-low seg-low Indirect Intersegment RET = Return from CALL: Within Segment Within Seg Adding lmmed to SP 11000011 11000010 data-low data-high 11111111 mod 1 0 1 r/m offset-high seg-high disp-high 11111111 mod 0 1 1 r/m offset-high seg-high disp-high 1111001z 1010010w 1010011w 1010111w 1010110w 1010101w 001100dw 1000000w 0011010w mod reg r/m mod 1 1 0 r/m data data data if w = 1 data if w = 1 000010dw 1000000w 0000110w mod reg r/m mod 1 0 1 r/m data data data if w = 1 data if w = 1 1000010w 1111011w 1010100w mod reg r/m mod 0 0 0 r/m data data data if w = 1 data if w = 1 0010000dw 1000000w 0010010w mod reg r/m mod 1 0 0 r/m data data data if w = 1 data if w = 1 76543210 110100vw 76543210 mod 0 1 1 r/m 76543210 76543210
3-30
80C88 Instruction Set Summary
(Continued) INSTRUCTION CODE MNEMONIC AND DESCRIPTION Intersegment Intersegment Adding Immediate to SP JE/JZ = Jump on Equal/Zero JL/JNGE = Jump on Less/Not Greater or Equal JLE/JNG = Jump on Less or Equal/ Not Greater JB/JNAE = Jump on Below/Not Above or Equal JBE/JNA = Jump on Below or Equal/Not Above JP/JPE = Jump on Parity/Parity Even JO = Jump on Overflow JS = Jump on Sign JNE/JNZ = Jump on Not Equal/Not Zero JNL/JGE = Jump on Not Less/Greater or Equal JNLE/JG = Jump on Not Less or Equal/Greater JNB/JAE = Jump on Not Below/Above or Equal JNBE/JA = Jump on Not Below or Equal/Above JNP/JPO = Jump on Not Par/Par Odd JNO = Jump on Not Overflow JNS = Jump on Not Sign LOOP = Loop CX Times LOOPZ/LOOPE = Loop While Zero/Equal LOOPNZ/LOOPNE = Loop While Not Zero/Equal JCXZ = Jump on CX Zero INT = Interrupt Type Specified Type 3 INTO = Interrupt on Overflow IRET = Interrupt Return PROCESSOR CONTROL CLC = Clear Carry CMC = Complement Carry STC = Set Carry CLD = Clear Direction STD = Set Direction CLl = Clear Interrupt ST = Set Interrupt HLT = Halt WAIT = Wait ESC = Escape (to External Device) LOCK = Bus Lock Prefix 11111000 11110101 11111001 11111100 11111101 11111010 11111011 11110100 10011011 11011xxx 11110000 mod x x x r/m 11001101 11001100 11001110 11001111 type 76543210 11001011 11001010 01110100 01111100 01111110 01110010 01110110 01111010 01110000 01111000 01110101 01111101 01111111 01110011 01110111 01111011 01110001 01111001 11100010 11100001 11100000 11100011 data-low disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp data-high 76543210 76543210 76543210
3-31
80C88 Instruction Set Summary
(Continued) INSTRUCTION CODE MNEMONIC AND DESCRIPTION NOTES: AL = 8-bit accumulator AX = 16-bit accumulator CX = Count register DS= Data segment ES = Extra segment Above/below refers to unsigned value. Greater = more positive; Less = less positive (more negative) signed values if d = 1 then "to" reg; if d = 0 then "from" reg if w = 1 then word instruction; if w = 0 then byte instruction if mod = 11 then r/m is treated as a REG field if mod = 00 then DISP = 0, disp-low and disp-high are absent if mod = 01 then DISP = disp-low sign-extended 16-bits, disp-high is absent if mod = 10 then DISP = disp-high:disp-low if r/m = 000 then EA = (BX) + (SI) + DISP if r/m = 001 then EA = (BX) + (DI) + DISP if r/m = 010 then EA = (BP) + (SI) + DISP if r/m = 011 then EA = (BP) + (DI) + DISP if r/m = 100 then EA = (SI) + DISP if r/m = 101 then EA = (DI) + DISP if r/m = 110 then EA = (BP) + DISP if r/m = 111 then EA = (BX) + DISP DISP follows 2nd byte of instruction (before data if required) except if mod = 00 and r/m = 110 then EA = disp-high: disp-low. MOV CS, REG/MEMORY not allowed. 76543210 76543210 76543210 76543210
if s:w = 01 then 16-bits of immediate data form the operand. if s:w = 11 then an immediate data byte is sign extended to form the 16-bit operand. if v = 0 then "count" = 1; if v = 1 then "count" in (CL) x = don't care z is used for string primitives for comparison with ZF FLAG.
SEGMENT OVERRIDE PREFIX
001 reg 11 0 REG is assigned according to the following table: 16-BIT (w = 1) 000 AX 001 CX 010 DX 011 BX 100 SP 101 BP 110 SI 111 DI 8-BIT (w = 0) 000 AL 001 CL 010 DL 011 BL 100 AH 101 CH 110 DH 111 BH SEGMENT 00 ES 01 CS 10 SS 11 DS
Instructions which reference the flag register file as a 16-bit object use the symbol FLAGS to represent the file: FLAGS = X:X:X:X:(OF):(DF):(IF):(TF):(SF):(ZF):X:(AF):X:(PF):X:(CF) Mnemonics (c) Intel, 1978
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